Integrated circuit devices, such as those used in computer systems, must communicate with one another. Differential signaling is often used in data transfer applications since it offers good signal integrity and common mode noise is rejected. Moreover, higher data-rates can be achieved with low swing signaling, as the equivalent swing at the differential receiver will be doubled. Those advantages come at the price of requiring transmitting both the true and the complimentary signals. Additionally, a more complex differential signal routing is required (two signals must be routed as close as possible and care must be taken in length matching).
It is common practice in wide parallel interfaces, such as memory interfaces, to make use of differential signaling for timing critical signals such as clocks or strobes, and to use single-ended signaling for data in order to keep the design compact and save board real estate. With this mixed approach the number of connections can generally be kept to a minimum.
Due to the different type of signaling employed in transmitting data and timing reference signals, special care must be taken in order to not disrupt the timing relationship between the signals. In order to match the latencies between the differential and single-ended receiver, the same type of receiver is typically used for receiving both the single-ended and differential signals. However, even if the same type of receiver is employed in receiving the two signals, a mismatch can occur. This, in turn, can result in requiring more frequent or even continuous calibration or clock resynchronization. Moreover, with such receivers, high gain receivers are often used, which increases power consumption.
For these and other reasons, there is a need for the present invention.